Modelling and Optimisation of the Turn-Off Switching Transition in Fast-Switching Power Semiconductor Devices
| dc.contributor.author | Du Toit, Francois Paulus | |
| dc.contributor.supervisor | Hofsajer, Ivan | |
| dc.date.accessioned | 2026-09-11T15:39:51Z | |
| dc.date.issued | 2025 | |
| dc.department | Electrical Engineering | |
| dc.description | A thesis submitted in fulfilment of the requirements for the degree of Doctor of Philosophy, to the Faculty of Engineering and the Built Environment, School of Electrical and Information Engineering, University of the Witwatersrand, Johannesburg, 2025 | |
| dc.description.abstract | The transition from Silicon to modern wide band gap semiconductor devices substantially increases the switching speed, enhancing the efficiency and energy density of power electronic converters. However, this increase in switching speed leads to a larger voltage overshoot across devices during turn-off due to the leakage inductance of the commutation path. While minimising the parasitic inductance is effective in solving this problem, it can never be entirely eliminated. This inductance induced overshoot already restricts the full potential of wide bandgap devices and will become an even greater challenge with the introduction of ultra-wide bandgap devices in the future. As this overshoot problem has existed almost since the inception of power electronics, several methods for reducing voltage overshoot have been reported in the literature. However, nearly all studies only present the experimental performance of their own results before and after the implementation of the over shoot suppression method and never compare the results to the existing body of results. Even though these experimental results and methods are difficult to compare due to varying testing conditions, not comparing results runs the risk of not being as successful or relevant as it is thought to be. In this work, a framework is developed that enables the comparison of results from the literature. This approach allows us to identify which methods are potentially more effective and should be given priority. Recent results from the literature are analysed using this framework with the conclusion that the emerging method of Zero Overvoltage Switching offers the most future potential for high-speed switching. In the literature, it has already been demonstrated that Zero Overvoltage Switching can reduce the voltage overshoot across a device as the parasitic inductance and switching speed increase, contrary to convention. However, the literature does not yet offer a sound theoretical foundation for this anomalous result, which limits its application. Additionally, the technique requires ideal switching and a very narrow range of circuit parameters to be implemented successfully, further limiting its application. This work investigates the underlying mechanisms of Zero Overvoltage Switching to firstly place the technique on a sound theoretical basis and secondly to show how the range of application might be increased to account for non-ideal switching and a wide range of circuit parameters. The turn-off switching transition of a clamped inductive load is investigated, explicitly modelling the adjustable turn-off current of the switch and in the presence of parasitic elements. The adjustable turn-off current of the switch is able to account for both fast and slow switching conditions. From the resulting model, it is seen that when switching slowly, the clamp diode conducts before the current in the switching device becomes zero, and it is this switching that describes the generally accepted understanding of the switching event. However, when switching very fast, the current in the device becomes zero before the clamp diode conducts, and this alternative order of events accounts for the unexpected results of Zero Overvoltage Switching. It is seen that these fast switching conditions require the ideal energy at the exact time the diode starts to conduct to eliminate the overvoltage. This is different from conventional soft switching, where there is an energy balance between the load inductor and snubber capacitances. This work provides the circuit-level analysis and the state progressions of both fast and slow switching by implementing circuit analysis and Laplace transforms to create a mathematical model to compare the two. This allows the mechanism of Zero Overvoltage Switching to become visible while still being able to explain the results of conventional switching. However, Zero Overvoltage Switching can only be implemented with ideal switching and with a very specific ratio and range of voltage and current. It is seen that if the turn-off current of the switch is modelled with two segments instead of one to represent the shaping of the turn-off waveform, the model shows that ideal switching is not required to effectively eliminate the overshoot and range of voltage and current where Zero Overvoltage Switching can take place is greatly expanded. Beyond addressing the specific problem of voltage over shoot, this research highlights a broader issue in power electronics: the field’s fragmented and application-driven nature has limited the development of fundamental, unifying knowledge. The findings of this work suggest that the constraints imposed by parasitic inductance may not be as fundamental as previously assumed. It also underscores a key point that the primary obstacle to realising the full potential of these devices lies in the development of advanced control methods rather than the increasingly challenging task of further reducing parasitic components. | |
| dc.description.submitter | MMM2026 | |
| dc.faculty | Faculty of Engineering and the Built Environment | |
| dc.identifier | 0009-0002-5397-619X | |
| dc.identifier.citation | Du Toit, Francois Paulus. (2025). Modelling and Optimisation of the Turn-Off Switching Transition in Fast-Switching Power Semiconductor Devices. [PhD thesis, University of the Witwatersrand, Johannesburg]. WIReDSpace. https://hdl.handle.net/10539/50038 | |
| dc.identifier.uri | https://hdl.handle.net/10539/50038 | |
| dc.language.iso | en | |
| dc.publisher | University of the Witwatersrand, Johannesburg | |
| dc.rights | ©2025 University of the Witwatersrand, Johannesburg. All rights reserved. The copyright in this work vests in the University of the Witwatersrand, Johannesburg. No part of this work may be reproduced or transmitted in any form or by any means, without the prior written permission of University of the Witwatersrand, Johannesburg. | |
| dc.rights.holder | University of the Witwatersrand, Johannesburg | |
| dc.school | School of Electrical and Information Engineering | |
| dc.subject | Silicon | |
| dc.subject | Zero Overvoltage Switching | |
| dc.subject | Turn-Off Switching Transition | |
| dc.subject | Fast-Switching Power Semiconductor Devices | |
| dc.subject | UCTD | |
| dc.subject.primarysdg | SDG-9: Industry, innovation and infrastructure | |
| dc.subject.secondarysdg | SDG-4: Quality education | |
| dc.title | Modelling and Optimisation of the Turn-Off Switching Transition in Fast-Switching Power Semiconductor Devices | |
| dc.type | Thesis |