Retaining the integrity of dc-link voltage in variable speed drives applications

Abstract

This research is concerned with the development of a power electronics module that utilises a switched capacitor for retaining the integrity of the dc-link voltage of a variable speed drive (VSD) during a short-term power interruption (STPI). Many industrial processes are now very much dependent on solid-state AC VSDs. Their susceptibility to voltage dips and STPIs, resulting in disruptions of critical processes, loss of production and revenue is a major concern. To support the transmission grid, power station equipment is required to withstand certain voltage disturbances anticipated on the transmission network. In South Africa, these requirements are specified in the South Africa Grid Code (SAGC). Non-compliance to SAGC requirements, production and revenue losses can be avoided by enhancing the voltage dip ride-through capability of the VSD. This research work only focuses on the worst-case voltage disturbance of a 0.2s STPI. Capacitor switching onto the dc-link was accompanied by an inrush current. To limit this current, the module was initially equipped with a fixed resistor. A method for sizing this resistor and capacitor for a v/f-controlled drive using readily available VSD and motor nameplate was developed and validated. The methodology is meant for low voltage (<1000V)and low power (100kW) applications. Simulation and experimental work were conducted for the validation of the proposed module. Fixed resistor inrush limiting experimental results show a 10.6% drop in torque and a 2.5% drop in speed with torque pulsations of 13% and 14% at start and end of compensation respectively. Module efficiency was estimated to be 94.8%. Fixed resistors resulted in an undesirable 7.7% voltage drop across the resistor and loss in efficiency which led to the investigation and development of a further three inrush current limiting techniques. These include, the use of a variable resistor, inductor and equipotential voltage switching. Variable resistor technique resulted in a 9.8% drop in torque and 1.7% drop in speed with torque pulsations of 12% and 9% at start and end of compensation respectively. Voltage drop between the dc-link and capacitor during compensation was reduced to 1.9%. An overall module efficiency of 99.3% was obtained. Use of an inductor resulted in a 10.1% drop in torque and 1.2% drop in speed with torque pulsations of 15% and 12% at start and end of compensation respectively. Module efficiency of 99.5% was obtained. Equipotential voltage switching resulted in the least voltage and torque drops of 9.9% and 3.2% respectively. It provided the highest estimated efficiency of 99.6%. Low torque pulsations of 6.8% and 9.8% at start and end of compensation respectively were observed. With this technique, considerable high frequency inverter currents flow through the capacitor resulting in the need of a capacitor with a higher ripple current rating. VSD and motor performance were found to be influenced by the inrush current limiting technique adopted. The proposed module did not eliminate the drop in dc-link voltage but ensured that the dc-link voltage remained above the VSD under-voltage trip level thereby allowing the VSD to ride-through the 0.2s STPI while supplying load power